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1 IPD050N10N5 rev.2.1,2017-01-17 final data sheet d-pak mosfet optimos tm 5power-transistor ,100v features ?n-channel,normallevel ?excellentgatechargex r ds(on) product(fom) ?verylowon-resistance r ds(on) ?175coperatingtemperature ?pb-freeleadplating;rohscompliant ?qualifiedaccordingtojedec 1) fortargetapplication ?idealforhigh-frequencyswitchingandsynchronousrectification ?halogen-freeaccordingtoiec61249-2-21 table1keyperformanceparameters parameter value unit v ds 100 v r ds(on),max 5.0 m w i d 80 a q oss 67 nc q g (0v..10v) 51 nc type/orderingcode package marking relatedlinks IPD050N10N5 p-to252-3 050n10n5 - 1) j-std20 and jesd22 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3
2 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet tableofcontents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3
3 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet 1maximumratings at t a =25c,unlessotherwisespecified table2maximumratings values min. typ. max. parameter symbol unit note/testcondition continuous drain current i d - - - - 80 80 a t c =25c 1) t c =100c pulsed drain current 1) i d,pulse - - 320 a t c =25c avalanche energy, single pulse 2) e as - - 110 mj i d =80a, r gs =25 w gate source voltage v gs -20 - 20 v - power dissipation p tot - - 150 w t c =25c operating and storage temperature t j , t stg -55 - 175 c iec climatic category; din iec 68-1: 55/175/56 2thermalcharacteristics table3thermalcharacteristics values min. typ. max. parameter symbol unit note/testcondition thermal resistance, junction - case r thjc - 0.6 1 k/w - thermal resistance, junction - ambient, minimal footprint r thja - - 75 k/w - thermal resistance, junction - ambient, 6 cm 2 cooling area 3) r thja - - 50 k/w - soldering temperature, wave and reflow soldering are allowed t sold - - 260 c reflow msl1 1) see diagram 3 for more detailed information 2) see diagram 13 for more detailed information 3) device on 40 mm x 40 mm x 1.5 mm epoxy pcb fr4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. pcb is vertical in still air. 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3
4 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet 3electricalcharacteristics table4staticcharacteristics values min. typ. max. parameter symbol unit note/testcondition drain-source breakdown voltage v (br)dss 100 - - v v gs =0v, i d =1ma gate threshold voltage v gs(th) 2.2 3.0 3.8 v v ds = v gs , i d =84a zero gate voltage drain current i dss - - 0.1 10 1 100 a v ds =100v, v gs =0v, t j =25c v ds =100v, v gs =0v, t j =125c gate-source leakage current i gss - 1 100 na v gs =20v, v ds =0v drain-source on-state resistance r ds(on) - - 4.3 5.1 5 6.7 m w v gs =10v, i d =40a v gs =6v, i d =20a gate resistance 1) r g - 1.2 1.8 w - transconductance g fs 48 95 - s | v ds |>2| i d | r ds(on)max , i d =40a table5dynamiccharacteristics 1) values min. typ. max. parameter symbol unit note/testcondition input capacitance c iss - 3600 4700 pf v gs =0v, v ds =50v, f =1mhz output capacitance c oss - 560 730 pf v gs =0v, v ds =50v, f =1mhz reverse transfer capacitance c rss - 25 44 pf v gs =0v, v ds =50v, f =1mhz turn-on delay time t d(on) - 13 - ns v dd =50v, v gs =10v, i d =40a, r g,ext =1.6 w rise time t r - 7 - ns v dd =50v, v gs =10v, i d =40a, r g,ext =1.6 w turn-off delay time t d(off) - 27 - ns v dd =50v, v gs =10v, i d =40a, r g,ext =1.6 w fall time t f - 7 - ns v dd =50v, v gs =10v, i d =40a, r g,ext =1.6 w table6gatechargecharacteristics 2) values min. typ. max. parameter symbol unit note/testcondition gate to source charge q gs - 16 - nc v dd =50v, i d =40a, v gs =0to10v gate to drain charge 1) q gd - 10 16 nc v dd =50v, i d =40a, v gs =0to10v switching charge q sw - 16 - nc v dd =50v, i d =40a, v gs =0to10v gate charge total 1) q g - 51 64 nc v dd =50v, i d =40a, v gs =0to10v gate plateau voltage v plateau - 4.5 - v v dd =50v, i d =40a, v gs =0to10v output charge 1) q oss - 67 89 nc v dd =50v, v gs =0v 1) defined by design. not subject to production test 2) see 2 gate charge waveforms 2 for parameter definition 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3
5 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet table7reversediode values min. typ. max. parameter symbol unit note/testcondition diode continous forward current i s - - 80 a t c =25c diode pulse current i s,pulse - - 320 a t c =25c diode forward voltage v sd - 0.9 1.2 v v gs =0v, i f =40a, t j =25c reverse recovery time 1) t rr - 48 96 ns v r =50v, i f = 40a ,d i f /d t =100a/s reverse recovery charge 1) q rr - 62 124 nc v r =50v, i f = 40a ,d i f /d t =100a/s 1) defined by design. not subject to production test 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3
6 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet 4electricalcharacteristicsdiagrams diagram1:powerdissipation t c [c] p tot [w] 0 50 100 150 200 0 25 50 75 100 125 150 175 p tot =f( t c ) diagram2:draincurrent t c [c] i d [a] 0 50 100 150 200 0 20 40 60 80 100 i d =f( t c ); v gs 3 10v diagram3:safeoperatingarea v ds [v] i d [a] 10 -1 10 0 10 1 10 2 10 3 10 0 10 1 10 2 10 3 1 s 10 s 100 s 1 ms 10 ms dc i d =f( v ds ); t c =25c; d =0;parameter: t p diagram4:max.transientthermalimpedance t p [s] z thjc [k/w] 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 -2 10 -1 10 0 10 1 0.5 0.2 0.1 0.05 0.02 0.01 single pulse z thjc =f( t p );parameter: d = t p / t 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3
7 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet diagram5:typ.outputcharacteristics v ds [v] i d [a] 0 1 2 3 4 5 0 40 80 120 160 200 240 280 320 360 7 v 8 v 10 v 6.5 v 6 v 5.5 v 5 v 4.5 v i d =f( v ds ); t j =25c;parameter: v gs diagram6:typ.drain-sourceonresistance i d [a] r ds(on) [m w ] 0 40 80 120 160 200 240 280 320 0 2 4 6 8 10 5 v 5.5 v 6 v 6.5 v 7 v 8 v 10 v r ds(on) =f( i d ); t j =25c;parameter: v gs diagram7:typ.transfercharacteristics v gs [v] i d [a] 0 2 4 6 8 0 30 60 90 120 150 180 175 c 25 c i d =f( v gs );| v ds |>2| i d | r ds(on)max ;parameter: t j diagram8:typ.forwardtransconductance i d [a] g fs [s] 0 40 80 120 160 0 40 80 120 160 200 g fs =f( i d ); t j =25c 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3
8 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet diagram9:drain-sourceon-stateresistance t j [c] r ds(on) [m w ] -60 -20 20 60 100 140 180 0 2 4 6 8 10 12 max typ r ds(on) =f( t j ); i d =40a; v gs =10v diagram10:typ.gatethresholdvoltage t j [c] v gs(th) [v] -60 -20 20 60 100 140 180 0 1 2 3 4 840 a 84 a v gs(th) =f( t j ); v gs = v ds ;parameter: i d diagram11:typ.capacitances v ds [v] c [pf] 0 20 40 60 80 100 10 1 10 2 10 3 10 4 ciss coss crss c =f( v ds ); v gs =0v; f =1mhz diagram12:forwardcharacteristicsofreversediode v sd [v] i f [a] 0.0 0.5 1.0 1.5 2.0 10 0 10 1 10 2 10 3 25 c 175 c 25 c, 98% 175 c, 98% i f =f( v sd );parameter: t j 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3
9 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet diagram13:avalanchecharacteristics t av [s] i av [a] 10 -1 10 0 10 1 10 2 10 3 10 0 10 1 10 2 25 c 100 c 150 c i as =f( t av ); r gs =25 w ;parameter: t j(start) diagram14:typ.gatecharge q gate [nc] v gs [v] 0 20 40 60 0 2 4 6 8 10 80 v 50 v 20 v v gs =f( q gate ); i d =40apulsed;parameter: v dd diagram15:drain-sourcebreakdownvoltage t j [c] v br(dss) [v] -60 -20 20 60 100 140 180 90 95 100 105 110 v br(dss) =f( t j ); i d =1ma 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3 gate charge waveforms
10 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet 5packageoutlines figure1outlinep-to252-3,dimensionsinmm/inches 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3 gate charge waveforms
11 optimos tm 5power-transistor ,100v IPD050N10N5 rev.2.1,2017-01-17 final data sheet revisionhistory IPD050N10N5 revision:2017-01-17,rev.2.1 previous revision revision date subjects (major changes since last revision) 2.0 2016-11-22 release of final version 2.1 2017-01-17 update idss max at tj=25c trademarksofinfineontechnologiesag aurix?,c166?,canpak?,cipos?,coolgan?,coolmos?,coolset?,coolsic?,corecontrol?,crossave?,dave?,di-pol?,drblade?, easypim?,econobridge?,econodual?,econopack?,econopim?,eicedriver?,eupec?,fcos?,hitfet?,hybridpack?,infineon?, isoface?,isopack?,i-wafer?,mipaq?,modstack?,my-d?,novalithic?,omnitune?,optiga?,optimos?,origa?,powercode?, primarion?,primepack?,primestack?,profet?,pro-sil?,rasic?,real3?,reversave?,satric?,sieget?,sipmos?,smartlewis?, solidflash?,spoc?,tempfet?,thinq?,trenchstop?,tricore?. trademarksupdatedaugust2015 othertrademarks allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. welistentoyourcomments anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com publishedby infineontechnologiesag 81726mnchen,germany ?2016infineontechnologiesag allrightsreserved. legaldisclaimer theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics (beschaffenheitsgarantie). withrespecttoanyexamples,hintsoranytypicalvaluesstatedhereinand/oranyinformationregardingtheapplicationofthe product,infineontechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithoutlimitation warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. inaddition,anyinformationgiveninthisdocumentissubjecttocustomerscompliancewithitsobligationsstatedinthis documentandanyapplicablelegalrequirements,normsandstandardsconcerningcustomersproductsandanyuseofthe productofinfineontechnologiesincustomersapplications. thedatacontainedinthisdocumentisexclusivelyintendedfortechnicallytrainedstaff.itistheresponsibilityofcustomers technicaldepartmentstoevaluatethesuitabilityoftheproductfortheintendedapplicationandthecompletenessoftheproduct informationgiveninthisdocumentwithrespecttosuchapplication. information forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestinfineon technologiesoffice( www.infineon.com ). warnings duetotechnicalrequirements,componentsmaycontaindangeroussubstances.forinformationonthetypesinquestion, pleasecontactthenearestinfineontechnologiesoffice. theinfineontechnologiescomponentdescribedinthisdatasheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofinfineontechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. 1 2 3 tab d r a i n p i n 2 , t a b g a t e p i n 1 s o u r c e p i n 3 gate charge waveforms

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